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1 for more information www.linear.com/ltm4647 typical application features description 30a dc/dc step-down module regulator the lt m ? 4647 is a complete 30 a output switching mode step-down dc/dc module ? ( power module) regulator. included in the package are the switching controller, power fets, inductor and all supporting components. operating over an input voltage range of 4.7 v to 15 v, the ltm4647 supports an output voltage range of 0.6 v to 1.8 v, set by a single external resistor. only a few input and output capacitors are needed. its high efficiency design delivers 87% efficiency from 12v input to 1.0 v output with 30 a continuous load current. high switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. the device supports frequency synchronization, programmable multiphase operation, n+1 phase redundancy, and output voltage tracking for supply rail sequencing. fault protection features include overvoltage and overcur - rent protection . the power module is offered in a space saving 9mm 15mm 5.01 mm bga package. the ltm4647 is available with snpb (bga) or rohs compli - ant terminal finish. 12v in , 1v out , 30a dc/dc module regulator applications n 4.7 v to 15v input voltage range n 0.6 v to 1.8v output voltage range n 30a dc output current n 1.2% total dc output voltage error (C40 c to 125c) n high reliability n + 1 phase redundancy supported n internal or external control loop compensation n differential remote sense amplifier for precision regulation n current mode control/fast transient response n multiphase current sharing up to 180a n built-in temperature monitoring n selectable pulse-skipping, burst mode ? operation n soft-start/voltage tracking n frequency synchronization n output overvoltage protection n output overcurrent foldback protection n 9mm 15mm 5.01mm bga package n telecom, networking and industrial equipment n point-of-load regulation l, lt , lt c , lt m , linear technology, the linear logo, burst mode, module, ltpowercad and polyphase are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. 1v out efficiency vs load current load current (a) *5v input see figure 24 0 efficiency (%) 80 4647 ta01b 70 10 20 5 15 25 90 100 75 65 85 95 30 5v input* 12v input hizb v in sv in freq compa compb track/ss pins not used in this circuit: clkout, mode/pllin, pgood, phasmd, pwm, run, sw, temp + , temp ? v out v osns + v fb v osns ? 22f 25v 2 2.2 4.7f 6.3v 1f 0.1f v in 6v to 15v 43.2k drv cc intv cc ltm4647 sgnd gnd 90.9k 4647 ta01a 100f 6.3v 6 47pf v out 1v 30a ltm 4647 4647fb
2 for more information www.linear.com/ltm4647 pin configuration absolute maximum ratings v in , sv in , hizb .......................................... C 0.3 v to 16 v v out , ......................................................... C0. 3 v to 3.5 v intv cc , drv cc , pgood , run ..................... C 0.3 v to 6v mode / pllin , track / ss , v osns + , v osns C , clkout , compa , compb , v fb , phasmd , freq .................................................... C 0.3 v to intv cc internal operating temperature range ( note 2) .... C4 0 to 125 c storage temperature range ...................... C 55 to 125 c peak solder reflow body temperature ................. 250 c temp + , temp C .......................................... C0. 3 v to 0.8 v (note 1) bga package 77-lead (9mm 15mm 5.01mm) 1 v in drv cc v out gnd gnd gnd l k j h g f e d c b a 2 3 4 gnd pwm clkout test1 mode/pllin phasmd intv cc freq sgnd test3 pgood compb gnd gnd sv in hizb gnd run 5 6 7 top view v fb v osns + compa test2 v osns ? temp ? temp + track/ss sw t j(max) = 125c, ja = 9.5c/w, jcbottom = 4c/w, jctop = 6.7c/w, jb = 4.5c/w ja derived from 95mm 76mm pcb with six layers; weight = 2g values determined per jesd51-12 part number pad or ball finish part marking* package type msl ra ting temperature range (note 2) device finish code lt m 4647ey#pbf sac305 (rohs) lt m 4647y e1 bga 3 C40c to 125c lt m 4647iy#pbf sac305 (rohs) lt m 4647y e1 bga 3 C40c to 125c lt m 4647iy snpb (63/37) lt m 4647y e0 bga 3 C40c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www. linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www . linear.com/umodule/pcbassembly ? lga and bga package and t ray drawings: www. linear.com/packaging order information http://www .linear.com/product/ltm4647#orderinfo ltm 4647 4647fb
3 for more information www.linear.com/ltm4647 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, per the typical application. symbol parameter conditions min typ max units v in input dc voltage v in = 4.7v to 6v per figure 24 schematic v in = 6v to 15v per figure 23 schematic l 4.7 15 v v out(range) output voltage range v in = 4.7v to 15v l 0.6 1.8 v v out(dc) output voltage, total variation with line and load c in = 22f 4, c out = 100f ceramic, 470 f poscap , r fb = 60.4k , mode = gnd ,v in = 4.7 v to 15v , i out = 0 a to 30a l 1.196 1.186 1.200 1.200 1.204 1.214 v v input specifications i q(vin) input supply bias current v in = 12v, v out = 1.2v, burst mode operation, i out = 0a v in = 12v, v out = 1.2v, pulse-skipping mode, i out = 0a v in = 12v, v out = 1.2v, switching continuous, i out = 0a shutdown, run = 0, v in = 12v 11 22 130 90 ma ma ma a i s(vin) input supply current v in = 12v, v out = 1.2v, i out = 30a 3.6 a output specifications i out(dc) output continuous current range v in = 12v, v out = 1.2v (note 4) 0 30 a ?v out(line) /v out line regulation accuracy v out = 1.2v, v in from 4.7v to 15v, i out = 0a l 0.005 0.02 %/v ?v out(load) / v out load regulation accuracy v out = 1.2v, i out = 0a to 30a, v in = 12v (note 4) l 0.1 0.3 % v out(ac) output ripple voltage c out = 100f ceramic 6, v in = 12v, v out = 1.2v, i out = 0a 15 mv ?v out(start) turn-on overshoot c out = 100f ceramic 6, v in = 12v, v out = 1.2v, i out = 0a 20 mv t start turn-on time c out = 100f ceramic 6 v in = 12v, v out = 1.2v, no load, track/ss = 0.01f 5 ms ?v outls peak deviation for dynamic load load: 0% to 50% to 0% of full load, c out = 100f ceramic 6, v in = 12v, v out = 1.2v 36 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load, c out = 100f ceramic 6, v in = 12v, v out = 1.2v 15 s i outpk output current limit v in = 12v, v out = 1.2v 34 a control specifications v fb voltage at v fb pin i out = 0a, v out = 1.2v l 597.5 595 600 600 602.5 605 mv i fb current at v fb pin (note 7) C30 C100 na i track/ss track pin soft-start pull-up current track/ss = 0v 1.25 a t on(min) minimum on-time (notes 3, 7) 90 ns r fbhi resistor between v out_lcl and v fb pins 60.05 60.40 60.75 k v run run pin on threshold v run rising 1.2 1.35 1.45 v v runhys run pin on hysteresis 180 mv uvlo undervoltage lockout v intvcc falling 4 v uvlo hys uvlo hysteresis 300 mv v hizb hizb pin on threshold v hizb rising 2.3 v v hizbhys hizb pin on hysteresis 800 mv ltm 4647 4647fb
4 for more information www.linear.com/ltm4647 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, per the typical application. symbol parameter conditions min typ max units pgood r pgood pgood pull-down resistance 90 200 v pgood pgood trip level v fb with respect to set output v fb ramping negative v fb ramping positive C7.5 7.5 % % v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v intv cc linear regulator v intvcc internal v cc voltage v in 12v 5.3 5.5 5.7 v v intvcc load reg intv cc load regulation i cc = 0ma to 10ma 0.5 % oscillator and phase-locked loop f sync sync capture range 400 800 khz f sw switching frequency r freq = 47.5k 540 600 660 khz i freq freq pin current v freq = 0.8v 20 a r mode_pllin mode_pllin input resistance 250 k v ih_mode_pllin clock input level high 2.0 v v il_mode_pllin clock input level low 1.2 v clkout clkout to sw phase delay v phsmd = 0v v phsmd = 1/4 intv cc v phsmd = float v phsmd = 3/4 intv cc v phsmd = intv cc 90 90 120 60 180 deg deg deg deg deg note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4647 is tested under pulsed load conditions such that t j t a . the ltm4647e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4647i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: the minimum on-time condition is specified for a peak-to-peak inductor ripple current of ~40% of i max load. (see the applications information section) note 4: see output current derating curves for different v in , v out and t a . note 5: limit current into the run pin to less than 2ma. note 6: guaranteed by design. note 7: 100% tested at wafer level. ltm 4647 4647fb
5 for more information www.linear.com/ltm4647 typical performance characteristics 0.8v output load stop transient response 1v output load step transient response 1.2v output load step transient response 1.5v output load step transient response efficiency vs output current, v in = 5v efficiency vs output current, v in = 12v ccm, burst mode and pulse- skipping mode efficiency v in = 12v, v out = 1.2v, 500khz load current (a) 0 efficiency (%) 100 95 85 80 90 75 65 70 20 10 25 4647 g01 30 15 5 0.8v out , 400khz 1v out , 500khz 1.2v out , 500khz 1.5v out , 600khz 1.8v out , 700khz load current (a) 0 efficiency (%) 100 95 85 80 90 75 65 70 20 10 25 4647 g02 30 15 5 0.8v out , 400khz 1v out , 500khz 1.2v out , 500khz 1.5v out , 600khz 1.8v out , 700khz load current (a) efficiency (%) 4647 g03 100 90 80 70 40 30 20 10 50 60 0 0.1 10 100 1 ccm burst mode operation pulse-skipping mode 4647 g07 v in = 12v, v out = 1.5v, f s = 600khz c out = 6 100f ceramic 0a to 7.5a load step, 10a/s 20s/div v out 50mv/div ac-coupled load step 10a/div sw 20v/div 1.8v output load step transient response 4647 g08 v in = 12v, v out = 1.8v, f s = 700khz c out = 6 100f ceramic 0a to 7.5a load step, 10a/s 20s/div v out 50mv/div ac-coupled load step 10a/div sw 20v/div 4647 g04 v in = 12v, v out = 0.8v, f s = 400khz c out = 6 100f ceramic 0a to 7.5a load step, 10a/s 20s/div v out 50mv/div ac-coupled sw 20v/div load step 10a/div 4647 g05 v in = 12v, v out = 1v, f s = 500khz c out = 6 100f ceramic 0a to 7.5a load step, 10a/s 20s/div v out 50mv/div ac-coupled load step 10a/div sw 20v/div 4647 g06 v in = 12v, v out = 1.2v, f s = 500khz c out = 6 100f ceramic 0a to 7.5a load step, 10a/s 20s/div v out 50mv/div ac-coupled load step 10a/div sw 20v/div ltm 4647 4647fb
6 for more information www.linear.com/ltm4647 typical performance characteristics start-up with 30a load applied start-up with no load applied 4647 g09 v in = 12v, v out = 1.2v, f s = 500khz, no load c out = 1 47f ceramic + 1 470f spcap c ss = 0.1f 20ms/div sw 10v/div v out 500m/div l in 200ma/div 4647 g10 v in = 12v, v out = 1.2v, f s = 500khz, no load c out = 1 47f ceramic + 1 470f spcap c ss = 0.1f 20ms/div sw 10v/div v out 500m/div l in 2a/div ltm 4647 4647fb
7 for more information www.linear.com/ltm4647 pin functions v in ( a1-a3, b1-b2, c1-c2): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. gnd ( a4, a7, b3, c3, c4, d1-d4, e2-e4, f2, f4, f6, g1- g4, h1-h5, j5-j7, k5-k7): ground pins for both input and output returns. all ground pins need to connect with large copper areas underneath the unit. run (a6): run control pin. a voltage above 1.35 v will turn on the module. this is a 1a pull-up current on this pin. once the run pin rises above the 1.35 v threshold the pull-up current increases to 5a. pwm (b4): control pwm three-state output signal. for monitor and test purpose only. do not drive this pin. clkout (b5): clock output with phase control using the phasmd pin to enable multiphase operation between devices. see the applications information section. test1, test2, test 3 ( b6, d5, f7): these pins are for module initial test purposes. please connect these pins to gnd with a large gnd copper area. mode/ pllin ( b 7): mode selection pin and external synchronization pin. connect this pin to sgnd to force the module into force continuous current mode ( ccm) of operation. connect to intv cc to enable pulse-skipping mode of operation. leaving the pin floating will enable burst mode operation. a clock on the pin will force the module into continuous current mode of operation and synchronized to the external clock applied to this pin. see the applications information section. sv in (d6): signal v in . input voltage to the internal 5.5v regulator for the control circuitry of the regulator. tie this pin to v in pin through a 2.2 plus 1 f r-c filter in most application. see the application information section. drv cc (c5): power input pin for the mosfet driver cir- cuitry. connect to intv cc output for the application with the input voltage 6 v and above or connect this pin to an external supply 4.5 v or above through a 2.2 plus 1f r-c filter. see the application information section. intv cc (c6): internal 5.5 v ldo for driving the control circuitry decouple with pin to gnd with a minimum of 2.2f low esr ceramic capacitor. the 5.5 v ldo has a 10ma current limit. phasmd (c7): this pin determines the relative phases between the internal controllers and the phasing of the clkout signal. see table 2 in the application informa- tion section. freq (d7): frequency set pin. a 20 a current is sourced from this pin. a resistor from this pin to ground sets a voltage that in turn programs the operating frequency. alternatively, this pin can be driven with a dc voltage that can set the operating frequency. see the applications information section. hizb (e5): phase shedding input pin. when this pin is low, track/ss, comp and pwm pin go to high impedance. tie to intv cc or v in to disable this function. v fb ( e6): the negative input of the error amplifier. inter- nally, this pin is connected to v osns + with a 60.4k 0.5% precision resistor. different output voltages can be pro- grammed with an additional resistor between v fb and v sns C pins. in polyphase ? operation, tying the v fb pins together allows for parallel operation. see the applications information section for details. sgnd (e7): signal ground pin. return ground path for all analog and low power circuitry. tie a single connection to the output capacitor gnd in the application. see layout guidelines in figure 22. sw (f3): switching node of the circuit is used for testing purposes. also an r-c snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. see the applications information section. track/ ss ( f 5): output voltage tracking pin and soft- start inputs. the pin has a 1.25 a pull-up current. a capacitor from this pin to ground will set a soft-start ramp rate. in tracking, the regulator output can be tracked to a different voltage. the voltage ramp rate at his pin sets the voltage ramp rate of the output. see the applications information section. package row and column labeling m ay vary among module products. review each package layout carefully. ltm 4647 4647fb
8 for more information www.linear.com/ltm4647 block diagram pin functions v osns C (g5): input to the remote sense amplifier. this pin connects to the ground remote sense point at the output load. v osns + ( g6): input to the remote sense amplifier. in- ternally, this pin is connected to v fb with a 60.4k 0.5% precision resistor. pgood ( g 7): output voltage power good indicator. open-drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regulation point. compa (h6): current control threshold and error am- plifier compensation point. the current comparator threshold increases with this control voltage. small filter capacitor (10 pf) internal to ltm4647 on this pin provides good noise rejection in the control loop. tie to compb pin to use internal compensation in the vast majority of applications. whereas, when more specialized applica - tions require an optimization of control loop response, connect an r-c compensation network from compa to sgnd. tie compa pins together in parallel operation. see the applications information section. compb ( h 7): internal loop compensation networks. tie to compa to provide internal loop compensation for majority of applications. float this pin if internal loop compensation not used. see compa description. v out ( j1-j4, k1-k4, l1-l7): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. see table 1. temp + ( f1): temperature monitor. an internal diode con- nected pnp transistor. see the applications information section. temp C (e 1): low side of the internal temperature monitor. figure 1. simplified ltm4647 block diagram + m1 0.12h m2 1f 60.4k 90.9k 4647 f01 r freq 47.5k v out c in c out gnd v sns ? v sns + v fb intv cc v in pgood clkout hizb run compa 2.2 compb intv cc power control 2.2f v in 6v to 15v v out 1v 30a + 10pf 0.1f 4.7f 0.1f 3300pf phasmd sv in 2k ? + diff amp freq sgnd intv cc intv cc dvrv cc track/ss mode/pllin 47pf 1f ltm 4647 4647fb
9 for more information www.linear.com/ltm4647 operation power module description the ltm4647 is a high performance single output stand- alone nonisolated switching mode dc/dc power supply. it can provide a 30 a output with few external input and output capacitors. this module provides precisely regu - lated output voltages programmable via external resistors from 0.6 v dc to 1.8 v dc over a 4.7 v to 15 v input range. the typical application schematic is shown in figure 23 and figure 24. the ltm4647 has an integrated constant-frequency cur- rent mode regulator, power mosfets , inductor, and other supporting discrete components. the switching frequency range is optimized from 400 khz to 700 khz, depending on output voltage. for switching noise- sensitive applications, it can externally program to or be synchronized to a clock from 400 khz to 800 khz subject to minimum on-time and inductor ripple current limitations. see the applications information section. the ltm4647 is designed to use either external or internal control loop compensation by shorting compb and compa pins together. with current mode control, the internal loop compensation has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors . table 5 provides a guideline for input and output capacitances for several different output conditions using the internal loop compensation . the ltpowercad ? design tool is available to download for optimizing the loop stability and transient response. current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. an internal overvoltage monitor protects the output voltage in the event of an overvoltage >10%. the top mosfet is turned off and the bottom mosfet is turned on until the output is cleared. pulling the run pin below 1.35 v forces the regulator into a shutdown state. the track/ss pin is used for pro- gramming the output voltage ramp and voltage tracking during start-up. see the application information section. multiphase operation can be easily employed by cascad - ing the mode/pllin input to the clkout output. see the applications information section and figure 25 for example. for high reliability environment, n+1 phase redundancy can be easily implemented in ltm4647 together with a hot swap controller, such as the lt c ? 4226, for extra system protection. by connecting the hizb pin to the gate of the hot swap switch, any fault channel can be disconnected while the rest of the system is not affected. see applica - tions information section and figure 27 for example. high efficiency at light loads can be accomplished with phase shedding in multiphase operation or with selectable pulse-skipping mode or burst mode operation in single phase operation. efficiency graphs are provided for light load operation in the typical performance characteristics section. a remote sense amplifier is provided for accurately sensing output voltages at the load point. a temp + and temp C pins are provided to allow the internal device temperature to be monitored using an onboard diode connected pnp transistor. decoupling requirements symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 4.7 v to 15 v, v out = 1v) i out = 30a 44 f c out external output capacitor requirement (v in = 4.7 v to 15 v, v out = 1v) i out = 30a 440 f ltm 4647 4647fb
10 for more information www.linear.com/ltm4647 applications information the typical ltm4647 application circuit is shown in figure?23 and figure 24. external component selection is primarily determined by the maximum load current and output voltage. refer to table 5 for specific external capacitor requirements for particular applications. v in to v out step-down ratios and minimum on-time there are restrictions in the v in to v out step-down ratio that can be achieved for a given input, output voltage and frequency. the minimum on-time, t on(min) , limits the smallest time duration that the module is capable of turning on the top mosfet. it is determined by internal timing delays, and the gate charge required turning on the top mosfet. at very low duty cycles, the minimum 90ns on-time must be maintained and satisfy the equation: t on = v out v in ?freq > 90ns if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the output ripple voltage of inductor ripple and current will increase. the minimum on-time can be increased by lowering the switching frequency. output voltage programming the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4k, 0.5% accuracy internal feedback resistor connects from the v sns + pin to the v fb pin. the output voltage will default to 0.6 v with no feedback resistor. adding a resistor r fb from v fb to v sns C programs the output voltage: v out = 0.6v ? 60.4k + r fb r fb table 1. v fb resistor table vs various output voltages v out (v) 0.6 0.8 1.0 1.2 1.5 1.8 r fb (k) open 182 90.9 60.4 40.2 30.1 frequency (khz) 400 400 500 500 600 700 r freq (k) 37.4 37.4 43.2 43.2 47.5 53.6 in multiphase single output application. only one set of differential sensing amplifier and one set of feedback resis- tor are required while connecting v out , v fb and comp of different channels together. see figure 25 for paralleling application. input capacitors the ltm4647 module should be connected to a low ac-impedance dc source. additional input capacitors are needed for the rms input ripple current rating. the i cin(rms) equation which follows can be used to calculate the input capacitor requirement. typically 22 f ceramics are a good choice with rms ripple current ratings of ~2a each. a 47 f to 100 f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance . this bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty cycle can be estimated as: d = v out v in without considering the inductor ripple current, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1Cd ( ) in the previous equation, % is the estimated efficiency of the power module. the bulk capacitor can be a switcher- rated electrolytic aluminum capacitor or a polymer capacitor. output capacitors the ltm4647 is designed for low output voltage ripple noise. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient require - ments. c out can be a low esr tantalum capacitor, low esr polymer capacitor or ceramic capacitors. please note small ltm 4647 4647fb
11 for more information www.linear.com/ltm4647 applications information 22pf to 47 pf feedforward capacitor (c ff ) is necessary for all ceramic output application to achieve enough phase margin. the typical output capacitance range is from 400f to 600 f. additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 7.5a/ s transient (at 10 a/s slew rate). the table optimizes total equivalent esr and total output capacitance to optimize the transient performance. multiphase operation will re - duce effective output ripple as a function of the number of phases. application note 77 discusses this reduction versus output ripple current cancellation. but the output capacitance should be considered carefully as a function of stability and transient response. the linear technology ltpowercad design tool can calculate the output ripple reduction as the number of implemented phase s increases by n times and provide stability analysis. burst mode operation the ltm4647 is capable of burst mode operation in which the power mosfets operate intermittently based on load demand, thus saving quiescent current. for applications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. to enable burst mode operation, simply float the mode_ pllin pin. during burst mode operation, the peak current of the inductor is set to approximately one-third of the maximum peak current value in normal operation even though the voltage at the compa pin indicates a lower value. the voltage at the compa pin drops when the inductors aver - age current is greater than the load requirement. as the compa voltage drops below 0.5 v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. the load current is now being supplied from the output capacitors. when the output voltage drops, causing compa to rise, the internal sleep line goes low, and the ltm4647 resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. pulse-skipping mode operation in applications where low output ripple and high efficiency at intermediate currents are desired, pulse - skipping mode should be used. pulse-skipping operation allows the ltm4647 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. tying the mode_pllin pin to intv cc enables pulse-skipping operation. with pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. this mode has lower ripple than burst mode operation and maintains a higher frequency operation than burst mode operation. forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode_pllin pin to gnd. in this mode, inductor current is allowed to reverse during low output loads, the compa voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start- up, forced continuous mode is disabled and inductor current is prevented from reversing until the ltm4647s output voltage is in regulation. frequency selection the ltm4647 device is operated over a range of frequencies to improve power conversion efficiency. it is recommended to operate the lower output voltages or lower duty cycle conversions at lower frequencies to improve efficiency by lowering power mosfet switching losses. higher output voltages or higher duty cycle conversions can be operated at higher frequencies to limit inductor ripple current. the efficiency graphs will show an operating frequency chosen for that condition. see table 1 for optimized frequency for various output voltages. the ltm4647 switching frequency can be set with an external resistor from the f set pin to sgnd. an accurate 20a current source into the resistor will set a voltage that programs the frequency or a dc voltage can be applied. figure 2 s hows a graph of frequency setting verses programming voltage. ltm 4647 4647fb
12 for more information www.linear.com/ltm4647 applications information pll and frequency synchronization for some switching noise sensitive applications, ltm4647 can be synchronized from 400khz to 800khz with an input clock that has a high level above 2 v and a low level below 0.8 v at the mode_ pllin pin. once the ltm4647 is syn - chronizing to an external clock frequency, it will always be running in forced continuous current operation. the 400khz low end operation frequency limit is put in place to limit inductor ripple current. multiphase operation for outputs that demand more than 30 a of load current, multiple ltm4647 devices can be paralleled to provide more output current without increasing input and output voltage ripple. the mode_pllin pin allows the ltm4647 to synchronize to an external clock (between 400 khz and 800 khz) and the internal phase-locked loop allows the ltm4647 to lock onto an incoming clock phase as well. the clkout signal can be connected to the mode_pllin pin of the following stage to line up both the frequency and the phase of the entire system. tying the phasmd pin to intv cc , three- fourths of intv cc , floating or, sgnd generates a phase difference ( between v out and clkout) of 180 degrees, 60 degrees , 120 degrees, 90 degrees respectively. a total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the phasmd pin of each ltm4647 channel to different levels. figure 3 shows a 2-phase, 3-phase, 4- phase, and 6- phase design example for clock phasing. v freq (v) 0.4 frequency (khz) 900 1100 1300 1.0 1.4 4647 f02 700 500 0.6 0.8 1.2 1.6 1.8 300 100 figure 2. relationship between switching frequency and freq pin voltage figure 3. phase selection examples ltm4647 180 phase mode_pllin phasmd clkout v out 3/4 intv cc ltm4647 240 phase mode_pllin phasmd clkout v out 3/4 intv cc ltm4647 300 phase mode_pllin phasmd 4647 f03 clkout v out 3/4 intv cc ltm4647 0 phase mode_pllin phasmd r2 10k r1 30.1k clkout v out ltm4647 0 phase mode_pllin phasmd clkout v out ltm4647 90 phase mode_pllin phasmd clkout v out ltm4647 180 phase mode_pllin phasmd clkout v out ltm4647 270 phase mode_pllin phasmd clkout v out 3/4 intv cc intv cc ltm4647 60 phase six phase four phase ltm4647 0 phase mode_pllin phasmd clkout v out ltm4647 120 phase mode_pllin phasmd clkout v out ltm4647 240 phase mode_pllin phasmd clkout v out three phase ltm4647 0 phase mode_pllin phasmd clkout v out ltm4647 180 phase mode_pllin phasmd clkout v out intv cc intv cc two phase mode_pllin phasmd clkout v out 3/4 intv cc ltm4647 120 phase mode_pllin phasmd clkout v out 3/4 intv cc v out phase 0 0 0 0 0 clkout phase 90 90 120 60 180 phasmd (v) 0 1/4 intv cc float 3/4 intv cc intv cc phase selection ltm 4647 4647fb
13 for more information www.linear.com/ltm4647 applications information the ltm4647 device is an inherently current mode con- trolled device , so parallel modules will have good current sharing. this will balance the thermals in the design. tie the compa, v fb , track/ss and run pins of each ltm4647 together to share the current evenly. figures 25 and 28 show a schematic of the parallel design. table 2. phasmd and clkout signal relationship phasmd gnd 1/4 intv cc float 3/4 intv cc intv cc clkout 90 90 120 60 180 a multiphase power supply could significantly reduce the amount of ripple current in both the input and output capacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used ( assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can - cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases (see figure 4). soft-start and output voltage tracking the track/ss pin provides a means to either soft-start the regulator or track it to a different power supply. a ca - pacitor on the track/ss pin will program the ramp rate of the output voltage. an internal 1.25 a current source will charge up the external soft-start capacitor towards intv cc voltage. when the track/ss voltage is below 0.6v, it will take over the internal 0.6 v reference voltage to control the output voltage. the total soft-start time can be calculated as: t ss = 0.6 ? c ss 1.25a 0.75 0.8 4647 f04 0.70.650.60.550.50.450.40.350.30.250.20.150.1 0.85 0.9 duty cycle (v out /v in ) 0 dc load current rms input ripple current 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 1 phase 2 phase 3 phase 4 phase 6 phase figure 4. normalized input rms ripple current vs duty cycle for one to six module regulators (phases) ltm 4647 4647fb
14 for more information www.linear.com/ltm4647 applications information where c ss is the capacitance on the track/ss pin. cur- rent foldback and forced continuous mode are disabled during the soft-start process. output voltage tracking can also be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. figure 5 and figure 6 show an example waveform and schematic of ratiometric tracking where the slave regulators output slew rate is proportional to the masters. figure 5. output ratiometric tracking waveform figure 6. example schematic of ratiometric output voltage tracking output voltage and the master output voltage should satisfy the following equation during start-up: v out(sl) ? r fb(sl) r fb(sl) + 60.4k = v out(ma) ? r tr(bot) r tr(top) + r tr(bot) the r fb(sl) is the feedback resistor and the r tr(top) / r tr(bot) is the resistor divider on the track/ss pin of the slave regulator, as shown in figure 6. following the previous equation, the ratio of the masters output slew rate ( mr) to the slaves output slew rate (sr) is determined by: mr sr = r fb(sl) r fb(sl) + 60.4k r tr(bot) r tr(top) + r tr(bot) for example, v out( ma) = 1.5v , mr = 1.5v /1ms and v out(sl) = 1.2 v, sr = 1.2 v/1ms, from the equation, we could solve that r tr(top) = 60.4 k and r tr(bot) = 40.2k are a good combination for the ratiometric tracking. the track/ss pin will have the 2.5 a current source on when a resistive divider is used to implement tracking on the since the slave regulators track/ss is connected to the masters output through a r tr(top) /r tr(bot) resistor divider and its voltage used to regulate the slave output voltage when track/ss voltage is below 0.6 v, the slave + v in hizb mode/pllin track/ss 22f 25v 2 4.7f 6.3v drv cc intv cc ltm4647 hizb sgnd gnd r fb(sl) 60.4k r tr(top) 60.4k r tr(bot) 40.2k 4647 f06 100f 6.3v 2 330f 6.3v 2 v out 1.2v 30a + v in hizb mode/pllin v out v osns + v fb v osns ? v out v osns + v fb v osns ? 22f 25v 2 4.7f 6.3v v in 6v to 15v drv cc sv in sv in intv cc ltm4647 hizb v in v in sgnd gnd r fb(ma) 40.2k 100f 6.3v 2 330f 6.3v 2 v out 1.5v 30a pins not used in these circuits: clkout, pgood, phasmd, run, sw 0.1f track/ss 1f 47.5k freq compa compb 47.5k freq compa compb 2.2 time slave output master output output voltage 4647 f05 ltm 4647 4647fb
15 for more information www.linear.com/ltm4647 applications information slave regulator. this will impose an offset on the track/ ss pin input. smaller value resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4 k is used then a 6.04 k can be used to reduce the track/ss pin offset to a negligible value. the coincident output tracking can be recognized as a special ratiometric output tracking in which the masters output slew rate ( mr) is the same as the slaves output slew rate (sr), waveform as shown in figure 7. in parallel operation the run pins can be tie together and controlled from a single control. the run pin can also be left floating. the run pin has a 1 a pull-up current source that increases to 5 a during ramp-up. please note that the run pin has an absmax voltage of 6v. differential remote sense amplifier an accurate differential remote sense amplifier is build into the ltm4647 to sense output voltages accurately at the remote load points. this is especially true for high current loads. it is very important that the v sns + and v sns C are connected properly at the remote output sense point , and the feedback resistor r fb is connected to between v fb pin to v sns C pin. review the schematics in figure 23 for reference. in multiphase single output application. only one set of differential sensing amplifier and one set of feedback resistor are required while connecting run, track/ss, v out , v fb and compa of different channels together. see figure 25 for paralleling application. power good the pgood pins are open-drain pins that can be used to monitor valid output voltage regulation. this pin monitors a 7.5% window around the regulation point. a resistor can be pulled up to a particular supply voltage no greater than 6v maximum for monitoring. overvoltage and overcurrent protection the ltm4647 has over current protection ( ocp) in a short circuit. the internal current comparator threshold folds back during a short to reduce the output current. an overvoltage condition ( ovp) above 7.5% of the regulated output voltage will force the top mosfet off and the bottom mosfet on until the condition is cleared. foldback cur - rent limit is disabled during soft-start or tracking start-up. pre-biased output start-up in the application that require the power supply to start up with a pre-bias on the output capacitors, the ltm4647 module can safely power up into a pre-biased output without discharging it. time master output slave output output voltage 4647 f07 figure 7. output coincident tracking waveform from the equation, we could easily find that, in coincident tracking, the slave regulator s track/ ss pin resistor divider is always the same as its feedback divider: r fb(sl) r fb(sl) + 60.4k = r tr(bot) r tr(top) + r tr(bot) for example, r tr(top) = 60.4 k and r tr(bot) = 60.4 k is a good combination for coincident tracking for a v out(ma) =1 .5v and v out(sl) = 1.2v application. run enable the run pin has an enable threshold of 1.45 v maximum, typically 1.35 v with 180 mv of hysteresis. it controls the turn-on of the module. the run pin can be pulled up to v in for 5 v operation, or a 5 v zener diode can be placed on the pin and a 10 k to 100 k resistor can be placed up to higher than 5 v input for enabling the module. the run pin can also be used for output voltage sequencing. ltm 4647 4647fb
16 for more information www.linear.com/ltm4647 applications information the ltm4647 accomplishes this by disabling both the top and bottom mosfets until the track/ss pin voltage and the internal soft- start voltage are above the v fb pin voltage. n+1 phase redundancy and hot swap the hizb pin can be used to force both top and bottom mosfet to turn off while not pulling down the compa and track/ss pins. in a multiphase system n+1 redundancy can be achieved via the hizb pin. when combined with a hot swap controller, such as the ltc4211, the hizb pin could be connected to the gate of the hot swap switch. when a damaged mosfet triggers the hot swap control - ler, it also disables the corresponding channels power, disconnecting it. since compa and track/ss pins are unaffected, it does not affect the rest of the system. the propagation delay from hizb falling to both top and bottom mosfet turned off is <200 ns. see figure 27 for example. sw pins and snubbering circuit the sw pin is generally for testing purposes by monitor - ing the pin. the sw pin can also be used to dampen out switch node ringing caused by lc parasitic in the switched current path. usually a series r-c combination is used called a snubber circuit. the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the power path board inductance in combination with the mosfet interconnect bond wire inductance. first the sw pin can be monitored with a wide bandwidth scope with a high frequency scope probe. the ring fre - quency can be measured for its value. the impedance z can be calculated: z l = 2 ? f ? l where f is the resonant frequency of the ring, and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. calculated by: z c = 1 2 ? f ?c these values are a good place to start. modification to these components should be made to attenuate the ring- ing with the least amount the power loss. stability compensation the ltm4647 has already been internally optimized and compensated for all output voltages and capacitor combi - nations including all ceramic capacitor applications when compb is tied to compa . please note that a 22 pf to 47pf feedforward capacitor (c ff ) is required connecting from v out to v fb pin for all ceramic capacitor application to achieve high bandwidth control loop compensation with enough phase margin . table 5 is provided for most application requirements using the optimized internal compensation. for specific optimized requirement, dis - connect compb from compa and apply a type ii c-r-c compensation network from compa to sgnd to achieve external compensation. the ltpowercad design tool is available to download online to perform specific control loop optimization and analyze the control stability and load transient performance. sv in , pv in , intv cc and drv cc sv in is the filtered input voltage to the internal 5.5 v ldo regulator to power the control circuitry of the regulator. connect sv in to v in through a 2.2 and 1f r-c filter. intv cc is the output of the 5.5 v ldo. decouple it with a minimum 2.2 f ceramic capacitor. connect intv cc to sv in directly if sv in is less than 6v. pv in is the power input connected to power mosfets and the drv cc is the supply voltage for the driver circuity to drive both power mosfets. drv cc could connect to an ltm 4647 4647fb
17 for more information www.linear.com/ltm4647 external supply higher than 4.5 v or v in (v in < 6 v) directly through a 2.2 plus 1 f r-c filter. in the application with the input voltage 6 v or above, drv cc could also connect to intv cc 5.5v output directly. see figure 23 for a typical application circuit for input 6v or above. see figure 24 for a typical application circuit for input from 4.7v to 5.5v. please note that intv cc and drv cc has 6 v absmax voltage rating. temperature monitoring measuring the absolute temperature of a diode is pos - sible due to the relationship between current, voltage and temperature described by the classic diode equation: i d = i s ? e v d ? v t ? ? ? ? ? ? or v d = ? v t ?in i d i s where i d is the diode current, v d is the diode voltage, is the ideality factor ( typically close to 1.0) and i s (satura- tion current) is a process dependent parameter. v t can be broken out to: v t = k ? t q where t is the diode junction temperature in kelvin, q is the electron charge and k is boltzmanns constant. v t is approximately 26 mv at room temperature (298 k) and scales linearly with kelvin temperature. it is this linear temperature relationship that makes diodes suitable tem- perature sensors. the i s term in the previous equation is the extrapolated current through a diode junction when the diode has zero volts across the terminals. the i s term varies from process to process, varies with temperature, applications information and by definition must always be less than i d . combining all of the constants into one term: k d = ?k q where k d = 8.62 ? 10 ?5 , and knowing ln(i d /i s ) is always positive because i d is always greater than i s , leaves us with the equation that: v d = t kelvin ( ) ?k d ?in i d i s where v d appears to increase with temperature. it is com- mon knowledge that a silicon diode biased with a current source has an approximate C2 mv/c temperature rela- tionship (figure 8), which is at odds with the equation. in fact, the i s term increases with temperature, reducing the ln(i d /i s ) absolute value yielding an approximate C2mv/c composite diode voltage slope. to obtain a linear voltage proportional to temperature we cancel the i s variable in the natural logarithm term to remove the i s dependency from the equation 1. this is accomplished by measuring the diode voltage at two cur- rents i 1 , and i 2 , where i 1 = 10 ? i 2 ) and subtracting we get: ?v d = t(kelvin)?k d ?in i 1 i s C t(kelvin)?k d ?in i 2 i s figure 8. diode voltage v d vs temperature t(c) temperature (c) ?50 ?25 0.3 diode voltage (v) 0.5 0.8 0 50 75 0.4 0.7 0.6 25 100 4647 f08 125 ltm 4647 4647fb
18 for more information www.linear.com/ltm4647 applications information combining like terms, then simplifying the natural log terms yields: ? v d = t(kelvin) ? k d ? ln(10) and redefining constant k' d = k d ?in(10) = 198v k yields ? v d = k' d ? t(kelvin) solving for temperature: t(kelvin) = ?v d k' d ( celsius) = t(kelvin)C 273.15 where 300 k = 27c means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198 v per kelvin of the junction with a zero intercept at 0 kelvin. the diode connected pnp transistor between the temp + and temp C pin can be used to monitor the internal tem- perature of the ltm4647. see figure 23 for an example. thermal considerations the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param- eters defined by jesd51-12 and are intended for use with finite element analysis ( fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on an module package mounted to a hardware test board. the motivation for providing these thermal coefficients in found in jesd 51-12 ( guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the module regulators thermal performance in their application at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a man - ner that yields insight and guidance pertaining to ones application usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd 51-12; these coefficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a 95mm 76mm pcb with six layers. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction- to- board thermal resistance where almost all of the heat flows through the bottom of the module package and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and a portion of the board. the board temperature is measured a specified distance from the package. ltm 4647 4647fb
19 for more information www.linear.com/ltm4647 applications information a graphical representation of the aforementioned ther- mal resistances is given in figure 9; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the ltm4647, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this 4647 f09 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction a t case (bottom)-to-board resistance figure 9. graphical representation of jesd51-12 thermal coefficients complication without sacrificing modeling simplicity but also not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reason - ably define and correlate the thermal resistance values supplied in this data sheet : (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4647 and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined jedec environment consistent with jesd51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values ; (3) the model and fea software is used to evaluate the ltm4647 with heat sink and airflow; (4) having solved for and analyzed these thermal resis - tance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operat - ing the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating curves shown in this data sheet . ltm 4647 4647fb
20 for more information www.linear.com/ltm4647 applications information the ltm4647 has been designed to effectively remove heat from both the top and bottom of the package. the bottom substrate material has very low thermal resistance to the printed circuit board. an external heat sink can be applied to the top of the device for excellent heat sinking with airflow. figures 10 and 11 show the thermal images of the ltm4647 with no heat sink and no airflow and 200 lfm airflow with 4.7w of internal dissipation. safety considerations the ltm4647 modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top mosfet fault. if the internal top mosfet fails, then turning it off will not resolve the overvoltage, thus the internal bottom mosfet will turn on indefinitely trying to protect the load. under this fault condition, the input voltage will source very large currents to ground through the failed internal top mosfet and enabled internal bot- tom mosfet . this can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. a fuse or circuit breaker can be used as a secondary fault protector in this situation. the device does support over current protection. the temp + and temp C pins are provided for monitoring internal tem- perature, and can be used to detect the need for thermal shutdown that can be done by controlling the hizb pin. output current derating the 1v, 1.5 v power loss curves in figures 12 to 13 can be used in coordination with the load current derating curves in figures 14 to 21 for calculating an approximate ja thermal resistance for the ltm4647 with various heat sinking and airflow conditions. the power loss curves are taken at room temperature and are increased with a multiplicative factor according to the junction temperature, which is 1.3 for 120 c. the derating curves are plotted with the output current starting at 30 a and the ambient temperature at ~40 c. the output voltages are 1 v and 1.5v. these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without airflow. the power loss increase with figure 10. ltm4647 12v in to 1v out at 30a with no air flow and no heat sink 4647 f10 figure 11. ltm4647 12v in to 1v out at 30a with 200lfm air flow and no heat sink 4647 f11 ltm 4647 4647fb
21 for more information www.linear.com/ltm4647 applications information figure 12. 1.0v power loss curve figure 13. 1.5v power loss curve figure 14. 12v to 1v derating curve, no heat sink figure 15. 5 v to 1 v derating curve, no heat sink figure 16. 12v to 1v derating curve, bga heat sink figure 17. 5v to 1v derating curve, bga heat sink figure 18. 12v to 1.5v derating curve, no heat sink figure 19. 5v to 1.5v derating curve, no heat sink load current (a) 0 power loss (w) 6 5 3 2 4 1 0 20 10 25 4647 f12 30 15 5 v in = 5v v in = 12v load current (a) 0 power loss (w) 6 5 3 2 4 1 0 20 10 25 4647 f13 30 15 5 v in = 5v v in = 12v ambient temperature (c) 30 load current (a) 35 30 20 15 25 10 5 0 80 50 60 90 100 110 4647 f14 120 70 40 0lmf 200lmf 400lmf ambient temperature (c) 30 load current (a) 35 30 20 15 25 10 5 0 80 50 60 90 100 110 4647 f15 120 70 40 0lmf 200lmf 400lmf ambient temperature (c) 30 load current (a) 35 30 20 15 25 10 5 0 80 50 60 90 100 110 4647 f16 120 70 40 0lmf 200lmf 400lmf ambient temperature (c) 30 load current (a) 35 30 20 15 25 10 5 0 80 50 60 90 100 110 4647 f17 120 70 40 0lmf 200lmf 400lmf ambient temperature (c) 30 load current (a) 35 30 20 15 25 10 5 0 80 50 60 90 100 110 4647 f18 120 70 40 0lmf 200lmf 400lmf ambient temperature (c) 30 load current (a) 35 30 20 15 25 10 5 0 80 50 60 90 100 110 4647 f19 120 70 40 0lmf 200lmf 400lmf ltm 4647 4647fb
22 for more information www.linear.com/ltm4647 applications information figure 20. 12v to 1.5v derating curve, bga heat sink figure 21 5v to 1.5v derating curve, bga heat sink table 3. 1.0v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 14, 15 5, 12 figure 12 0 none 9 figures 14, 15 5, 12 figure 12 200 none 6.5 figures 14, 15 5, 12 figure 12 400 none 6 figures 16, 17 5, 12 figure 12 0 bga heat sink 8.5 figures 16, 17 5, 12 figure 12 200 bga heat sink 5.5 figures 16, 17 5, 12 figure 12 400 bga heat sink 5 table 4. 1.5v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 18, 19 5, 12 figure 13 0 none 9 figures 18, 19 5, 12 figure 13 200 none 6.5 figures 18, 19 5, 12 figure 13 400 none 6 figures 20, 21 5, 12 figure 13 0 bga heat sink 8.5 figures 20, 21 5, 12 figure 13 200 bga heat sink 5.5 figures 20, 21 5, 12 figure 13 400 bga heat sink 5 heat sink manufacturer part number website aavid thermalloy 375424b00034g www.aavid.com cool innovations 4-050503p to 4-050508p www.coolinnovations.com ambient temperature (c) 30 load current (a) 35 30 20 15 25 10 5 0 80 50 60 90 100 110 4647 f20 120 70 40 0lmf 200lmf 400lmf ambient temperature (c) 30 load current (a) 35 30 20 15 25 10 5 0 80 50 60 90 100 110 4647 f21 120 70 40 0lmf 200lmf 400lmf ltm 4647 4647fb
23 for more information www.linear.com/ltm4647 applications information table 5. output voltage response vs component matrix (refer to figure 23) 0a to 7a load step typical measured values c in vendors value part number c out vendors value part number bulk panasonic sp-cap 470f 2.5v eefsx0e471e4 panasonic poscap 470f 2.5v 2r5tpd470m5 panasonic poscap 470f 6.3v 6tpd470m5 ceramic taiyo yuden 22f, 25v, 1206, x7s c3216x7s0j226m murata 100f, 6.3v, 1206, x5r grm31cr60j107m murata 22f, 25v,1206, x5r grm31cr61e226ke15l tdk 100f, 6.3v, 1206, x5r c3216x5r0g107m murata 220f, 4v, 1206, x5r grm31cr60g227m taiyo yuden 220f, 2.5v, 1206, x5r pmk316dbj227mlht ceramic cap only v in (v) v out (v) c in (ceramic) c out (ceramic) c out (bulk) c ff (pf) droop (mv) p -p devia tion (mv) recovery time (s) load step (a) slew ra te (a/s) r fb (k) freq (khz) 5, 12 0.8 22 f 3 100f 6 n/a 47pf 0 125 20 7 10 182 400 5, 12 1 22f 3 100f 6 n/a 47f 0 125 20 7 10 90.9 500 5, 12 1.2 22f 3 100f 6 n/a 47f 0 135 20 7 10 60.4 500 5, 12 1.5 22f 3 100f 6 n/a 47f 0 150 20 7 10 40.2 600 5, 12 1.8 22f 3 100f 6 n/a 47f 0 165 20 7 10 30.1 700 bulk and ceramic cap v in (v) v out (v) c in (ceramic) c out (ceramic) c out (bulk) c ff (pf) droop (mv) p -p devia tion (mv) recovery time (s) load step (a) slew ra te (a/s) r fb (k) freq (khz) 5, 12 0.8 22 f 3 47f 470f n/a 0 127 30 7 10 182 400 5, 12 1 22f 3 47f 470f n/a 0 140 30 7 10 90.9 500 5, 12 1.2 22f 3 47f 470f n/a 0 175 35 7 10 60.4 500 5, 12 1.5 22f 3 47f 470f n/a 0 185 40 7 10 40.2 600 5, 12 1.8 22f 3 47f 470f n/a 0 190 40 7 10 30.1 700 ltm 4647 4647fb
24 for more information www.linear.com/ltm4647 applications information ambient temperature change is factored into the derating curves. the junctions are maintained at ~120 c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operating temperature specifies how much module temperature rise can be allowed, as an example, in figure?14 the load current is derated to ~26a at ~80 c with no air or heat sink and the power loss for the 12 v to 1.0 v at 26 a output is about 4.6 w. the 4.6w loss is calculated with the ~3.6 w room temperature loss from the 12 v to 1.0 v power loss curve at 26 a, from figure 21, and the 1.3 multiplying factor at 120 c junction. if the 80c ambient temperature is subtracted from the 120 c junction temperature, then the difference of 40 c divided by 4.6 w equals a 8.8c/w ja thermal resistance. table 3 specifies a 9 c/w value which is very close. table 3 provides equivalent thermal resistances for 1.0 v and 1.5v outputs with and without airflow and heat sinking. the de - rived thermal resistances in tables 3 and 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the ef - ficiency cur ves in the typical performance characteristics section and adjusted with the above ambient temperature multiplicative factors. the printed circuit board is a 1.6mm thick six layer board with two ounce copper for all layers. the pcb dimensions are 95mm 76 mm. the bga heat sinks are listed in table 4. layout checklist/example the high integration of ltm4647 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout consid - erations are still necessary. ? use large pcb copper areas for high current paths, including v in , gnd, and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the v out , v fb , and comp pins together. use an internal layer to closely connect these pins together. the track pin can be tied a common capacitor for regulator soft-start. ? bring out test points on the signal pins for monitoring. figure 22 gives a good example of the recommended layout. ltm 4647 4647fb
25 for more information www.linear.com/ltm4647 figure 22. recommended pcb layout applications information gnd gnd 4647 f22 v in v out c in c out ltm 4647 4647fb
26 for more information www.linear.com/ltm4647 typical applications figure 23. typical 6v to 15v input 1.0v at 30a output design figure 24. typical 4.7v to 5.5v input 1.2v at 30a output design v in hizb track/ss compa compb freq pgood v out v osns + v fb v osns ? gnd sgnd mode/pllin drv cc intv cc sv in run ltm4647 22f 16v 2 100f 6.3v 6 v in 6v to 15v 0.1f 4.7f 1f v out 1v 30a 43.2k 2.2 100k 90.9k 4647 f23 pgood pins not used in this circuit: clkout, phasmd, pwm, sw 47pf temp + temp ? digital telemetry for temperature monitoring v in hizb drv cc track/ss compa compb freq pgood v out v osns + v fb v osns ? gnd sgnd temp + temp ? mode/pllin intv cc sv in run ltm4647 22f 16v 2 0.1f 47f 6.3v v in 4.7v to 5.5v v out 1.2v 30a 43.2k 100k 2.2 4647 f24 pgood 470f 6.3v digital telemetry for temperature monitoring pins not used in this circuit: clkout, phasmd, pwm, sw 60.4k 1f 4.7f ltm 4647 4647fb
27 for more information www.linear.com/ltm4647 typical applications figure 25. 6v to 15v input, 1.0v output at 60a v in hizb run track/ss compa compb freq sv in pgood v out v osns + v fb v osns ? gnd sgnd temp + temp ? clkout mode/pllin phmode drv cc intv cc ltm4647 u1 22f 25v 2 22f 25v 2 47f 6.3v 2 v in 6v to 15v 0.1f 4.7f v out 1v 60a 43.2k 100k 90.9k pgood fb sv in v in hizb run track/ss compa compb freq pgood v out v fb v osns ? gnd sgnd mode/pllin drv cc intv cc ltm4647 u2 4.7f 43.2k 4647 f25 pgood fb pins not used in circuit ltm4647 u1: pwm, sw pins not used in circuit ltm4647 u2: clkout, phasmd, pwm, sw, v osns + 470f 4v temperature monitoring temperature monitoring temp + temp ? 47f 6.3v 2 470f 4v 1f 2.2 ltm 4647 4647fb
28 for more information www.linear.com/ltm4647 typical applications figure 26. 6v to 15v input, 1.0v and 1.2v output with tracking v in hizb track/ss compa compb freq sv in pgood v out v osns + v fb v osns ? gnd sgnd mode/pllin drv cc intv cc ltm4647 22f 25v 2 47f 6.3v 2 v in 6v to 15v 0.1f 4.7f 470f 4v v out1 1v 30a 43.2k 100k 90.9k pgood1 sv in v in hizb track/ss compa compb freq pgood v out v osns + v fb v osns ? gnd sgnd mode/pllin drv cc intv cc ltm4647 22f 25v 2 47f 6.3v 2 4.7f 470f 4v v out2 1.2v 30a 43.2k 90.9k 60.4k 100k 60.4k 4647 f25 pgood2 pins not used in ltm4647 u1 and u2 circuits: clkout, phasmd, pwm, sw, temp + , temp ? run run 1f 2.2 ltm 4647 4647fb
29 for more information www.linear.com/ltm4647 typical applications figure 27. 3-phase 1v at 90a design with extra 1 phase 30a redundancy sv in v in hizb run track/ss compa compb freq v out v osns + v fb v osns ? gnd sgnd clkout phasmd drv cc intv cc ltm4647 u1 intv cc1 intv cc2 intv cc3 intv cc4 clk12 clk23 clk34 clk12 clk23 clk34 pin not used in circuit ltc4352cdd u7, u8, u9, u10: status hizb1 hizb2 hizb3 hizb4 22f 25v 2 22f 25v 2 1f 4.7f 6.3v 4.7f 6.3v 100f 6.3v 2 r fb6 60.4k 43.2k sv in v in hizb run track/ss compa compb freq v out v fb v osns ? gnd sgnd clkout phasmd mode/pllin drv cc intv cc ltm4647 u2 100f 6.3v 2 43.2k fb fb sv in v in hizb run track/ss compa compb freq v out v fb v osns ? gnd sgnd clkout phasmd mode/pllin drv cc intv cc ltm4647 u3 4.7f 6.3v 100f 6.3v 2 43.2k fb sv in v in hizb run track/ss compa compb freq v out v fb v osns ? gnd sgnd phasmd mode/pllin drv cc intv cc ltm4647 u4 pins not used in circuit ltm4647 u4: clkout, pgood, pwm, sw temp + , temp ? , v osns + pins not used in circuit ltm4647 u3: pgood, pwm, sw temp + , temp ? , v osns + pins not used in circuit ltm4647 u2: pgood, pwm, sw temp + , temp ? , v osns + pins not used in circuit ltm4647 u1: mode/pllin, pgood, pwm, sw, temp + , temp ? 4.7f 6.3v 100f 6.3v 2 0.1f 4647 f27 43.2k fb 10k v cc1 sense1 gate1 out1 v cc2 sense2 gate2 out2 on1 on2 cls gnd ftmr1 fault1 fault2 ftmr2 hizb1 1n448hwt 1n448hwt intv cc1 intv cc2 hizb2 10k r58 10k ltc4226cud-1 100pf 100pf 38.3k 0.007 2.2 fdms86500dc fdms86500dc 0.007 4.7f 25v v in 6v to 15v bus 21 cmhz4701 30.1k 2.4m 2 cmhz4683 10k v cc1 sense1 gate1 out1 v cc2 sense2 gate2 out2 on1 on2 cls gnd ftmr1 fault1 fault2 ftmr2 hizb3 1n448hwt 1n448hwt intv cc3 intv cc4 hizb4 10k r46 10k ltc4226cud-1 100pf 100pf 38.3k 0.007 fdms86500dc fdms86500dc 0.007 4.7f 25v 21 cmhz4701 30.1k 2.4m 2 cmhz4683 11 8 1210 4 1 3 4 6 13972 rev uv ov v cc rev gnd ep v in cpo source gate out hizb1 intv cc1 ltc4352cdd u7 r183 100 0.1f q1 bsc010ne2ls 1f 11 8 1210 4 1 3 4 6 13972 rev uv ov v cc rev gnd ep v in cpo source gate out hizb2 intv cc2 ltc4352cdd u8 r184 100 0.1f q7 bsc010ne2ls v out 1v 90a 1f 11 8 1210 4 1 3 4 6 13972 rev uv ov v cc rev gnd ep v in cpo source gate out fault fault fault fault hizb3 intv cc3 ltc4352cdd u9 r185 100 0.1f q8 bsc010ne2ls 1f 11 8 1210 4 1 3 4 6 13972 rev uv ov v cc rev gnd ep v in cpo source gate out hizb4 intv cc4 ltc4352cdd u10 r186 100 0.1f q9 bsc010ne2ls 1f 22f 25v 2 22f 25v 2 330f 6.3v 6 ltm 4647 4647fb
30 for more information www.linear.com/ltm4647 typical applications figure 28. 4 phase 1v at 120a design v in hizb run track/ss compa compb freq sv in pgood v out v osns + v fb v osns ? gnd sgnd clkout mode/pllin phasmd drv cc intv cc ltm4647 u1 22f 25v 8 v in 6v to 15v 2.2f 100f 6.3v 6 v out 1.0v 120a 100k 90.9k 43.2k comp pgood sv in v in hizb run track/ss compa compb freq pgood v out v fb v osns ? gnd sgnd clkout mode/pllin phasmd drv cc intv cc ltm4647 u2 2.2f 100f 6.3v 6 43.2k pgood fb fb sv in v in hizb run track/ss compa compb freq pgood v out v fb v osns ? gnd sgnd clkout mode/pllin phasmd drv cc intv cc ltm4647 u3 2.2f 100f 6.3v 6 43.2k pgood fb sv in v in hizb run track/ss compa compb freq pgood v out v fb v osns ? gnd sgnd mode/pllin phasmd drv cc intv cc ltm4647 u4 u4 pins not used: clkout, pwm, sw temp + , temp ? , v osns + u3 pins not used: pwm, sw temp + , temp ? , v osns + u2 pins not used: pwm, sw temp + , temp ? , v osns + u1 pins not used: pwm, sw temp + , temp ? hizb4 2.2f 100f 6.3v 6 0.1f 4647 f28 43.2k pgood fb 22pf 1f 2.2 ltm 4647 4647fb
31 for more information www.linear.com/ltm4647 package description ltm4647 component bga pinout pin id function pin id function pin id function pin id function pin id function pin id function a1 v in b1 v in c1 v in d1 gnd e1 temp C f1 temp + a2 v in b2 v in c2 v in d2 gnd e2 gnd f2 gnd a3 v in b3 gnd c3 gnd d3 gnd e3 gnd f3 sw a4 gnd b4 pwm c4 gnd d4 gnd e4 gnd f4 gnd a5 gnd b5 clkout c5 drv cc d5 test2 e5 hizb f5 track/ss a6 run b6 test1 c6 intv cc d6 sv in e6 v fb f6 gnd a7 gnd b7 mode/pllin c7 phasmd d7 freq e7 sgnd f7 test3 pin id function pin id function pin id function pin id function pin id function g1 gnd h1 gnd j1 v out k1 v out l1 v out g2 gnd h2 gnd j2 v out k2 v out l2 v out g3 gnd h3 gnd j3 v out k3 v out l3 v out g4 gnd h4 gnd j4 v out k4 v out l4 v out g5 v osns C h5 gnd j5 gnd k5 gnd l5 v out g6 v osns + h6 compa j6 gnd k6 gnd l6 v out g7 pgood h7 compb j7 gnd k7 gnd l7 v out package photo ltm 4647 4647fb
32 for more information www.linear.com/ltm4647 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description package top view 4 pin ?a1? corner y x aaa z aaa z bga package 77-lead (15.00mm 9.00mm 5.01mm) (reference ltc dwg# 05-08-1900 rev d) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (77 places) detail b substrate a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 77 a2 d e // bbb z z h2 h1 bga 77 0113 rev d tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module detail a package bottom view 3 see notes a b c d e f g h j k l pin 1 e b f g 7 6 5 4 3 2 1 suggested pcb layout top view 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 0.025 ? 77x 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes please refer to http://www .linear.com/product/ltm4647#packaging for the most recent package drawings. ltm 4647 4647fb
33 for more information www.linear.com/ltm4647 revision history rev date description page number a 12/16 changed v out(dc) min from 1.97 to 1.96 and max from 1.203 to 1.204 3 b 05/17 changed mls rating from 4 to 3 2 ltm 4647 4647fb
34 for more information www.linear.com/ltm4647 ? linear technology corporation 2016 lt 0517 rev b ? printed in usa www.linear.com/ltm4647 related parts part number description comments ltm4627 15a module regulator 4.5v v in 20v , 0.6v v out 5v , 15mm 15mm 4.32mm ( lga), 15mm 15mm 4.92mm ( bga) ltm4637 20a module regulator 4.5v v in 20v , 0.6v v out 5.5v , 15mm 15mm 4.32mm ( lga), 15mm 15mm 4.92mm ( bga) ltm4636 40a module regulator, 1.3% v out accuracy 4.75v v in 15v, 0.6v v out 3.3v, 16mm 16mm 7.12mm (bga) ltm4631 dual 10a, single 20a module regulator, 1.91mm package height 4.5v v in 15v. 0.6v v out 1.8v, 16mm x 16mm 1.91mm (lga) ltm4620a dual 13a or single 26a module regulator, v out 5.3v 4.5v v in 15v , 0.6v v out 5.3v , 15mm 15mm 4.41mm ( lga), 15mm 15mm 5.01mm ( bga) ltm4630 dual 18a or single 36a module regulator 4.5v v in 15v , 0.6v v out 1.8v , 16mm 16mm 4.41mm ( lga), 16mm 16mm 5.01mm ( bga) ltm4630a dual 18a or single 36a module regulator v out 5.3v 4.5v v in 15v, 0.6v v out 5.3v, 16mm 16mm 4.41mm (lga) ltm4630-1 dual 18a or single 36a module regulator 0.8v v out accuracy (C1a), external compensation 4.5v v in 15v, 0.6v v out 1.8v, 16mm 16mm 5.01mm (bga) LTM4650 dual 25a or single 50a module regulator 4.5v v in 15v, 0.6v v out 1.8v, 16mm 16mm 5.01mm (bga) LTM4650-1 dual 25a or single 50a module regulator 0.8v v out accuracy (C1a), external compensation 4.5v v in 15v, 0.6v v out 1.8v, 16mm 16mm 5.01mm (bga) ltm4675 dual 9a or single 18a module regulator with psm 4.5v v in 17v, 0.5v v out 5.5v, 16mm 11.9mm 3.51mm (bga) ltm4676a dual 13a or single 26a module regulator with psm 4.5v v in 17v, 0.5v v out 5.5v, 16mm 16mm 5.01mm (bga) ltm4677 dual 25a or single 50a module regulator with psm 4.5v v in 16v, 0.5v v out 1.8v, 16mm 16mm 5.01mm (bga) design resources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products sear ch 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power sear ch parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. ltm 4647 4647fb

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